FIG. 1 shows a conventional multiprocessor system 10 with distributed interrupt control. The system 10 includes four processors (CPUs) CPU1, CPU2, CPU3 and CPU4 each coupled to a CPU bus 12 and interrupt bus 16. The system 10 further includes I/O controller 14 coupled to the interrupt bus 16. The I/O controller 14 directs the transfer of data to and from peripheral devices such as displays, printers and disk drives. Each of the CPUs and the I/O controller 14 have an embedded Advanced Programmable Interrupt Controller (APIC) associated therewith coupled to the interrupt bus 14. Each APIC includes a hardware state machine for processing interrupt requests in a conventional manner. For example, the APIC of I/O controller 14 broadcasts interrupts to all of the CPUs over the interrupt bus 16. A problem with the distributed interrupt control of system 10 is that each of the CPUs and I/O controller must include a separate APIC, which unduly increases the cost and complexity of the system.
FIG. 2 shows a conventional multiprocessor system 20 with centralized interrupt control. The system 20 includes four processors (CPUs) CPU1, CPU2, CPU3 and CPU4 coupled to a CPU bus 22, and a Multiple Processor Interrupt Controller (MPIC) 24 coupled to a Peripheral Component Interconnect (PCI) bus 26 and an interrupt bus 25. The CPU bus 22 and PCI bus 26 are interconnected by a CPU-to-PCI bus bridge 28 which regulates the bidirectional flow of data between the PCI bus 26 and CPU bus 22. The MPIC 24 dispatches a given interrupt to the appropriate destination CPU of the interrupt rather than broadcasting the interrupt to all CPUs. The MPIC is generally configured such that only the current highest priority interrupt is dispatched at any particular time. An exemplary MPIC is described in greater detail in Donald W. McCauley, "Power PC Multiprocessor Interrupt Controller (MPIC)," IBM Power Personal Systems, Austin Tex., pp. 1-22, Aug. 14, 1995, which is incorporated by reference herein.
The multiprocessor systems 10 and 20 of FIGS. 1 and 2 are referred to as symmetrical multiprocessor systems because each of the CPUs CPU1, CPU2, CPU3 and CPU4 has the ability to receive and process interrupt requests. For example, the MPIC 24 in system 20 receives all of the interrupt requests, and dispatches them to the appropriate CPUs such that the interrupt requests are processed evenly across the CPUs. The above-cited IBM reference includes a specification referred to as OpenPIC which facilitates this type of multiprocessor interrupt processing. In accordance with the OpenPIC specification, each interrupt request has a destination register, a vector register and a priority register associated therewith. The destination register is used to identify which CPUs can service a particular interrupt request, the vector register holds the starting address in system memory of the interrupt service routine for the particular interrupt request, and the priority register indicates the relative priority of the particular interrupt request. In operation, the MPIC 24 detects an interrupt signal from an I/O device coupled to the PCI bus 26, and determines which CPU or CPUs to which the corresponding interrupt request should be dispatched using the information in the above-noted destination register. A CPU to which the interrupt is dispatched detects the interrupt request, reads the interrupt vector to determine the starting address of the interrupt service routine, and executes the interrupt service routine.
A number of significant problems limit the efficiency of conventional multiprocessor interrupt controllers such as MPIC 24 of FIG. 2. For example, a conventional interrupt controller can usually select and dispatch only the current highest priority interrupt request at a given time. After the current highest priority interrupt request is dispatched, but before it is received and accepted by the destination CPU, the interrupt controller will generally prevent the selection and dispatch of any further interrupt requests. It is therefore usually not possible to dispatch multiple interrupt requests simultaneously to different destination CPUs. Moreover, the current highest priority interrupt may be blocked because all of its possible destination CPUs are busy either handling interrupt requests or performing other tasks having a higher priority than the current highest priority interrupt. Conventional interrupt controllers are unable to mask blocked interrupt requests that cannot be dispatched so as to avoid preventing the selection and dispatch of non-blocked interrupt requests. These problems substantially undermine the efficiency of conventional interrupt controllers and thereby degrade the performance of multiprocessor systems which include such interrupt controllers.
As is apparent from the above, there is a need for a multiprocessor interrupt controller in which multiple interrupt requests can be dispatched simultaneously to different destination CPUs, and in which blocked interrupt requests which cannot be dispatched at a particular time are masked to thereby allow the selection and dispatch of non-blocked interrupt requests.